搜索资源列表
fir48
- 48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
1
- verilog编写的11阶FIR数字滤波器-The 11 order FIR digital filter Verilog prepared!!!!!!!!!!!!!!!!!!!!!
8fir
- 这是一个verilog语言描述的8阶fir滤波器-8firFILTERdesign
high-pass-filter-design
- 基于verilog的高通fir数字滤波器设计-Verilog fir digital high-pass filter design based on
FIR32
- 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
filter
- 大神写的FIR滤波器，verilog所写，短小精悍，易读懂！-Great God wrote the FIR filter, verilog written, short and pithy, easy to read!
firfilterverilog
- FIR FILTER DESIGNED IN VERILOG FOR 4 BIT MULTIPLIER
book3e
- 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
Digital-signal-process-of-PFGA
- 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
FIRfilterverilogHDL
- FIR滤波器的verilog HDL代码示例，以16阶为例-Verilog HDL code for fir filter
filter_FIR
- fir filter is made in the verilog
FIR_16bits_LP
- This is a verilog code for Low pass FIR Filter which inputs 16bit wide.
1M_200k_-firstandard
- 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
dac_900
- DAC900芯片驱动的Verilog语言描述，亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用，也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
FIR_filter
- 基于FPGA实现FIR滤波器功能 使用芯片为EP2C8Q208C8N,实现FIR滤波器的设计，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。-FIR filter function based on FPGA chip to use EP2C8Q208C8N, achieve FIR filter design using Verilog language programming, the present examples are engineering doc
DIGITAL-SIGNAL-PROCESSING-WITH-FPGA
- 数字信号处理的FPGA实现最新版的源代码，涉及FFT变换、IIR、FIR数字滤波器等的verilog及vhdl代码-<digital signal processing with FPGA> (the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
project_fir_test
- 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
dfe_filter
- DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
firfilterPfpga
- FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench